Early response to plasma/charging damage by special pattern design of active region

ABSTRACT

A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET&#39;s.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to the fabrication of integratedcircuit devices, and more particularly, to a method of early detectionof plasma/charging damage in the fabrication of integrated circuitdevices.

[0003] (2) Description of the Prior Art

[0004] The manufacture of large scale integrated circuits involveshundreds of processing steps. Most of these processing steps involvedepositing layers of material, patterning them by photolithographictechniques, and etching away the unwanted portions. Plasma etchingprocesses are often used because they are dry processes and they providethe cleanliness and degree of control required in integrated circuitmanufacture.

[0005] The most important semiconductor device in current technology isthe metal-oxide-silicon field effect transistor (MOSFET). This deviceconsists of two shallow regions of one type semiconductor—the source anddrain—seperated by a region of another type—the channel region. A gateelectrode overlies the channel region and is separated from it by a thingate oxide layer. This thin gate oxide layer is one of the most criticalcomponents of the MOSFET. Typically, the gate oxide layer is thermallygrown silicon oxide having a thickness on the order of 70-150 Angstromsin the current 0.25 micron design rule. An insulating film this thin ishighly susceptible to damage such as from ion and electron bombardmentfrom plasmas during backend processing. Plasma-induced degradation ofgate oxide reliability is a key issue in achieving high performanceMOSFET's.

[0006] The multiple exposures of gate oxides to steps involving plasmashas led to the emergence of several test structures designed to amplifythe charging exposure and thereby allow proper and timely assessment ofdamage caused by the plasma processing steps. Plasma damage teststructures are discussed in Silicon Processing for the VLSI Era, Vol. 3,by S. Wolf, Lattice Press, Sunset Beach, Calif. (1995) pp. 507-9. Theconventional test structures fall into one of two categories: 1) antennastructures which have large areas of conductor exposed to plasma ascompared to area of gate oxide, and 2) large area capacitors which areformed over the gate oxide. In addition, both types of structures may beeither edge-intensive or area-intensive. However, it is difficult forthese structures to catch plasma-induced damage in a timely manner ifthe damage is very slight.

[0007] A number of patents have addressed the plasma-induced damageissue. U.S. Pat. No. 5,650,651 to Bui discloses a plasma damagereduction device. U.S. Pat. No. 5,781,445 describes a plasma damage teststructure consisting of a MOSFET surrounded by a conductive shieldgrounded to the substrate. U.S. Pat. No. 5,596,207 to Krishnan et aldiscloses a modified MOS structure having conductive sidewalls over agate used to test for plasma damage. U.S. Pat. No. 5,638,006 to Narianiet al teaches the use of a testing structure that can differentiate weakoxide from charge-damaged oxide using an antenna structure.

SUMMARY OF THE INVENTION

[0008] Accordingly, it is a primary object of the invention to provide areliable and very manufacturable method for detecting plasma damage to agate oxide layer in the fabrication of integrated circuit devices.

[0009] A further object of the invention is to provide a process forearly and effective detection of plasma damage to a gate oxide layer.

[0010] Another object is to provide a process for early and effectivedetection of plasma damage to a gate oxide layer by a special design ofthe active region.

[0011] Yet another object is to provide a testing structure for earlyand effective detection of plasma damage to a gate oxide layer having aspecial design of the active region.

[0012] In accordance with the objects of the invention, a method ofearly and effective detection of plasma damage to a gate oxide layer bya special design of the active region is achieved. A plasma-damagetesting structure is fabricated by providing a gate electrode overlyingan active area of a semiconductor substrate wherein a gate oxide layerunderlies the gate electrode. A portion of the active area underlyingthe gate electrode has sharp corners. The plasma-damage testingstructure is exposed to a plasma environment. Electrical tests areperformed to detect plasma damage to the plasma-damage testingstructure. This model provides an accurate evaluation of slight plasmadamage to actual MOSFET's.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the accompanying drawings forming a material part of thisdescription, there is shown:

[0014]FIG. 1 is a top-view representation of a testing structure of theprior art.

[0015]FIG. 2 is a representation of the difference in sensitivity of aprior art testing structure and the testing structure of the presentinvention.

[0016]FIGS. 3A through 3F are top-view representations of preferredembodiments of the special active regions of the present invention.

[0017]FIGS. 4A through 4F are top-view representations of preferredembodiments of the plasma damage testing structure of the presentinvention.

[0018]FIG. 5 is a cross-sectional representation of a gate structure tobe simulated by the testing structure of the invention.

[0019]FIG. 6 is a top-view of the gate structure to be simulated by thetesting structure of the invention shown in cross-section in FIG. 5.

[0020]FIG. 7 is a top view of a preferred embodiment of the testingstructure of the present invention showing plasma damage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Referring now to FIG. 1, there is illustrated a conventionalplasma-damage testing structure of the prior art. Active area 10 isshown. Field oxide area 12 has been formed over the semiconductorsubstrate in the active area. Polysilicon gate 16 is shown within theactive area. The gate oxide layer, not shown, underlies and is coveredby the polysilicon gate 16.

[0022]FIG. 2 illustrates the degree of plasma-induced damage to the gateoxide shown across the top of the figure where no damage occurs to theleft of line 22. Increasing damage is shown to the right of line 22 inthe direction of the arrow 24. Slight damage occurs immediately to theright of line 22. With a testing structure of the prior art, such asthat shown in FIG. 1, there is a large “blind spot” 26 where damageoccurs, but is not revealed by the testing structure. Greater damage tothe right of the blind spot 26 can be caught by the testing structure.

[0023] In contrast, with the testing structure of the present invention,there is only a small blind spot 28. Damage to the right of the blindspot 28 is revealed by the testing structure of the invention. Thus, theinvention provides a more sensitive testing structure. Slight plasmadamage that cannot be detected by the old method can be detected withthe new method. This model allows an accurate evaluation ofplasma/charging damage of actual MOSFET's for the future VLSI era.

[0024] The process of the present invention for forming plasma-induceddamage testing structures will now be described. FIGS. 3A through 3Fillustrate top views of various possible configurations of the specialactive region patterns of the invention. The active area is defined, forexample, by a silicon nitride hard mask. The area outside andsurrounding the active area comprises field oxide.

[0025] The special pattern is applied to the active region 30. Thespecial pattern consists of an indentation in or a protuberance from therectangular part of the active area, as shown in FIGS. 3A-3F. Thus, theactive area has. sharp corners or edges. This pattern enhances thedegree of plasma damage to the active region caused by the residualstress from the edges or corners of the active area.

[0026] For example, the active area patterns shown in FIGS. 3A-3F have arectangular shape in top view. An indentation is cut into or aprotuberance is formed out of the rectangular part of the active area.The indentation may have a rectangular shape as shown in FIG. 3A,inwardly sloping sidewalls with a flat bottom as shown in FIG. 3B, or aV-shape as shown in FIG. 3C. The protuberance may have a rectangularshape as shown in FIG. 3D, outwardly sloping sidewalls with a flat topas shown in FIG. 3E, or an inverted V-shape as shown in FIG. 3F. Othershapes having sharp corners are possible.

[0027] A gate oxide layer is formed over the active area. A conductionlayer is deposited over the gate oxide layer. The conduction layer andgate oxide layer are patterned to form the gate pattern 32 on the activeregion, as shown in FIGS. 4A-4F. The conduction layer may be polysiliconor a metal, for example.

[0028] These testing structures can now be used for both edge-intensiveand area-intensive plasma-damage monitoring. Wafers having these testingstructures are exposed to a plasma environment. During exposure to aplasma environment, electron charge punches through the gate oxide(underlying the gate 32) to the substrate. Thus, pinholes will be formedin the gate oxide due to the plasma charge. Next, electrical tests areperformed to calculate the degree of plasma damage.

[0029] For example, FIGS. 5 and 6 illustrate a MOSFET to be modeled bythe test structure of the invention. In the figures, polysilicon gate 56overlies a gate oxide layer 54 and a field oxide region 52 in and on asemiconductor substrate 50. FIG. 5 shows the cross-section 5-5 of thetop view shown in FIG. 6. Damage to the gate oxide layer 54 is oftenseen near the edge of the FOX region 52 as indicated by 58 in the twofigures.

[0030]FIG. 7 illustrates in top view the testing structure of thepresent invention to be used to monitor plasma damage for the structureof the MOSFET example shown in FIGS. 5 and 6. 30 is the active areapattern used in the testing structure. The active area pattern has sharpcorners which will enhance the degree of plasma damage to the teststructure. The dashed line 36 indicates the real active area shape ofthe MOSFET. 32 is the gate pattern comprising a conductive layeroverlying a gate oxide layer. The x's 38 shown in FIG. 7 indicate weakpoints due to stress during field oxide formation. Even very slightdamage to the gate oxide layer can be detected by the test structures ofthe invention.

[0031] The process of the present invention applies a special activeregion pattern as a plasma damage sensor. This sensor will monitorplasma/charging damage earlier and more effectively than the prior arttesting structures. The testing structures of the invention use anactive region pattern having sharp corners that enhances the degree ofplasma damage by the residual stress from the edges or corners of theactive region. This allows slight damage that cannot be caught by theprevious methods to be detected, allowing for an early response toplasma damage.

[0032] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of forming a plasma-damage testingstructure comprising: providing a gate electrode overlying an activearea of a semiconductor substrate wherein a gate oxide layer underliessaid gate electrode and wherein a portion of said active area underlyingsaid gate electrode has sharp corners to complete said plasma-damagetesting structure wherein said plasma-damage testing structure willsimulate plasma damage to said gate oxide layer in the fabrication of anintegrated circuit device.
 2. The method according to claim 1 whereinsaid sharp corners cause residual stress in said active area whichenhances the degree of plasma damage to said active area.
 3. The methodaccording to claim 1 wherein said active area has a rectangular shape intop view having an indentation cut into said rectangular shape whereinsaid indentation has sharp corners.
 4. The method according to claim 3wherein said indentation has a rectangular shape in top view.
 5. Themethod according to claim 3 wherein said indentation has a V-shape intop view.
 6. The method according to claim 3 wherein said indentationhas a shape having inward sloping sidewalls and a flat bottom in topview.
 7. The method according to claim 1 wherein said active area has arectangular shape in top view having an protuberance out of saidrectangular shape wherein said protuberance has sharp corners.
 8. Themethod according to claim 7 wherein said protuberance has a rectangularshape in top view.
 9. The method according to claim 7 wherein saidprotuberance has an inverted V-shape in top view.
 10. The methodaccording to claim 7 wherein said protuberance has a shape havingoutward sloping sidewalls and a flat top in top view.
 11. A method ofdetecting plasma damage comprising: fabricating a plasma-damage testingstructure comprising providing a gate electrode overlying an active areaof a semiconductor substrate wherein a portion of said active areaunderlying said gate electrode has sharp corners; exposing saidplasma-damage testing structure to a plasma environment; and performingelectrical tests to detect plasma damage to said plasma-damage testingstructure.
 12. The method according to claim 11 wherein said sharpcorners cause residual stress in said active area which enhances thedegree of plasma damage to said active area.
 13. The method according toclaim 11 wherein said active area has a rectangular shape in top viewhaving an indentation cut into said rectangular shape wherein saidindentation has sharp corners.
 14. The method according to claim 11wherein aid active area has a rectangular shape in top view having anprotuberance out of said rectangular shape wherein said protuberance hassharp corners.
 15. A method of detecting plasma damage comprising:fabricating a plasma-damage testing structure comprising providing agate electrode overlying an active area of a semiconductor substratewherein a gate oxide layer underlies said gate electrode and wherein aportion of said active area underlying said gate electrode has sharpcorners; exposing said plasma-damage testing structure to a plasmaenvironment; and performing electrical tests to detect plasma damage tosaid plasma-damage testing structure.
 16. The method according to claim15 wherein said sharp corners cause residual stress in said active areawhich enhances the degree of plasma damage to said gate oxide layer. 17.The method according to claim 15 wherein said active area has arectangular shape in top view having an indentation cut into saidrectangular shape wherein said indentation has sharp corners.
 18. Themethod according to claim 15 wherein said active area has a rectangularshape in top view having an protuberance out of said rectangular shapewherein said protuberance has sharp corners.
 19. A plasma-damage testingstructure comprising: a gate electrode overlying an active area of asemiconductor substrate wherein a gate oxide layer underlies said gateelectrode and wherein a portion of said active area underlying said gateelectrode has sharp corners.
 20. The plasma-damage testing structureaccording to claim 19 wherein said plasma-damage testing structure willsimulate plasma damage to said gate oxide layer in the fabrication of anintegrated circuit device.